| CPC H10B 12/50 (2023.02) [H10B 12/395 (2023.02); H10B 12/482 (2023.02); H10N 70/231 (2023.02); H10N 70/841 (2023.02)] | 20 Claims |
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1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit;
a second semiconductor structure comprising:
an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor; and
a plurality of bit lines coupled to the memory cells, and a major axis of each of the plurality of bit lines extending in a second direction perpendicular to the first direction,
wherein;
a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction; and
two adjacent vertical transistors of the vertical transistors in the second direction are mirror-symmetric to one another, each of the two adjacent vertical transistors comprising a respective semiconductor body, each semiconductor body corresponding to only one gate structure at one side of the semiconductor body and in direct contact with a trench isolation at two sides of the trench isolation, and in the second direction, the semiconductor bodies being separated by the trench isolation; and
a bonding interface between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface.
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