US 12,349,334 B2
Semiconductor structure and method for manufacturing same
Semyeong Jang, Hefei (CN); Joonsuk Moon, Hefei (CN); and Deyuan Xiao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 22, 2022, as Appl. No. 17/934,558.
Application 17/934,558 is a continuation of application No. PCT/CN2022/101503, filed on Jun. 27, 2022.
Claims priority of application No. 202210644418.0 (CN), filed on Jun. 8, 2022.
Prior Publication US 2023/0019926 A1, Jan. 19, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/05 (2023.02) [H10B 12/315 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate comprising discrete semiconductor channels arranged at a top of the substrate and extending along a vertical direction;
a gate structure being disposed in a middle region of each of the semiconductor channels and comprising a ring structure and a bridge structure, the ring structure encircling the semiconductor channel, the bridge structure penetrating through the semiconductor channel and extending to an inner wall of the ring structure along a penetrating direction;
a cover layer located in a spacer region between adjacent semiconductor channels, the cover layer comprising a first communication hole extending along the vertical direction; and
a first sacrificial structure located on the cover layer, the first sacrificial structure comprising a second communication hole extending along the vertical direction, the second communication hole being in communication with a top of the semiconductor channel via the first communication hole, an inner sidewall of the second communication hole having an irregular shape.