US 12,349,330 B2
Shared pick-up regions for memory devices
Chih-Chuan Yang, Hsinchu (TW); Chao-Yuan Chang, New Taipei (TW); Shih-Hao Lin, Hsinchu (TW); Chia-Hao Pao, Kaohsiung (TW); Feng-Ming Chang, Zhubei (TW); Lien-Jung Hung, Taipei (TW); and Ping-Wei Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 28, 2022, as Appl. No. 17/731,781.
Prior Publication US 2023/0354573 A1, Nov. 2, 2023
Int. Cl. H01L 21/78 (2006.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); H10B 10/00 (2023.01); G06F 30/3953 (2020.01); H10D 84/85 (2025.01)
CPC H10B 10/18 (2023.02) [G06F 30/392 (2020.01); G06F 30/398 (2020.01); H10B 10/125 (2023.02); G06F 30/3953 (2020.01); H10D 84/854 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A memory structure, comprising:
a memory cell array comprising:
a plurality of memory cells; and
a plurality of first n-type wells extending in a first direction;
a second n-type well formed in a peripheral region of the memory structure, wherein the second n-type well extends in a second direction and is in contact with one of the plurality of first n-type wells; and
a pick-up region formed in the second n-type well, wherein the pick-up region is electrically coupled to the one of the plurality of first n-type wells via a second pick-up region.