US 12,349,282 B2
Capacitors in through glass vias
Benjamin Duong, Chandler, AZ (US); Aleksandar Aleksov, Chandler, AZ (US); Helme A. Castro De La Torre, Gilbert, AZ (US); Kristof Darmawikarta, Chandler, AZ (US); Darko Grujicic, Chandler, AZ (US); Sashi S. Kandanur, Phoenix, AZ (US); Suddhasattwa Nad, Chandler, AZ (US); Srinivas V. Pietambaram, Chandler, AZ (US); Rengarajan Shanmugam, Chandler, AZ (US); Thomas L. Sounart, Chandler, AZ (US); and Marcel Wall, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/482,399.
Prior Publication US 2023/0091666 A1, Mar. 23, 2023
Int. Cl. H05K 1/18 (2006.01); H01G 4/33 (2006.01); H05K 1/03 (2006.01); H05K 1/11 (2006.01)
CPC H05K 1/185 (2013.01) [H01G 4/33 (2013.01); H05K 1/0306 (2013.01); H05K 1/115 (2013.01); H05K 2201/09545 (2013.01); H05K 2201/096 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A capacitor comprising:
a glass layer with a first side and a second side opposite the first side;
a through glass via (TGV) that extends from the first side of the glass layer to the second side of the glass layer;
a first conductive layer on a wall of the TGV;
a dielectric layer on the first conductive layer within the TGV, wherein the dielectric layer has an end with a top surface at a same level as a top surface of an end of the first conductive layer; and
a second conductive layer on the dielectric layer within the TGV, wherein the first conductive layer and the second conductive layer are electrically isolated from each other.