US 12,348,626 B2
Integrated circuit (IC) signatures with random number generator and one-time programmable device
Shih-Lien Linus Lu, Hsinchu (TW); Kun-Hsi Li, Hsinchu (TW); Shih-Liang Wang, Hsinchu (TW); Jonathan Tsung-Yung Chang, Hsinchu (TW); Yu-Der Chih, Hsinchu (TW); and Cheng-En Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 2, 2024, as Appl. No. 18/624,646.
Application 18/624,646 is a continuation of application No. 18/064,098, filed on Dec. 9, 2022, granted, now 11,962,693.
Application 18/064,098 is a continuation of application No. 17/106,856, filed on Nov. 30, 2020, granted, now 11,528,135.
Claims priority of provisional application 63/002,676, filed on Mar. 31, 2020.
Prior Publication US 2024/0348435 A1, Oct. 17, 2024
Int. Cl. H04L 9/08 (2006.01); G06F 7/58 (2006.01); H04L 9/32 (2006.01)
CPC H04L 9/0869 (2013.01) [G06F 7/584 (2013.01); H04L 9/0877 (2013.01); H04L 9/0897 (2013.01); H04L 9/3278 (2013.01); H04L 2209/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A physical unclonable function (PUF) device comprising:
a substrate;
an input address block arranged on the substrate, the input address block configured to receive and randomize a challenge to generate an input request;
a one-time programmable device (OTP) arranged on the substrate, wherein the OTP is communicatively coupled to the input address block to receive the input request;
a random number generator arranged on the substrate and communicatively coupled to the OTP to provide a string of random numbers, the random number generator including a static random access memory (SRAM) that is read, after initialization, to provide a plurality of bits, and a liner-feedback shift register (LFSR) to scramble the plurality of bits read from the SRAM into scrambled key bits; and
a controller arranged on the substrate and communicatively coupled to both the OTP and the random number generator, the controller configured to start the SRAM of the random number generator and write the scrambled key bits from the LFSR to the OTP,
wherein the OTP is configured to store the scrambled key bits, provided from the LFSR; associate the scrambled key bits with an address; receive a scrambled address from an input address scrambler; determine the address, associated with the scrambled key bits, which matches the scrambled address; read the scrambled key bits having the address that matches the scrambled address; and provide the scrambled key bits as a security key.