US 12,348,382 B2
Incremental topology modification of a network-on-chip
Benoit de Lescure, Campbell, CA (US); and Moez Cherif, Santa Cruz, CA (US)
Assigned to ARTERIS, INC., Campbell, CA (US)
Filed by ARTERIS, INC., Campbell, CA (US)
Filed on Apr. 9, 2024, as Appl. No. 18/631,033.
Application 18/631,033 is a continuation of application No. 17/686,364, filed on Mar. 3, 2022, granted, now 11,956,127, issued on Apr. 9, 2024.
Claims priority of provisional application 63/158,890, filed on Mar. 10, 2021.
Prior Publication US 2024/0259274 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 41/14 (2022.01); G06F 15/78 (2006.01)
CPC H04L 41/145 (2013.01) [G06F 15/7825 (2013.01)] 1 Claim
OG exemplary drawing
 
1. A computer-implemented method for generation of an updated topology, the method comprising:
receiving an update to an initial Network-on-Chip (NoC) topology, wherein the update results in updated requirements to initial requirements of the NoC;
modifying a portion of the initial NoC topology that is impacted by the update in order to satisfy the update and generate an incremental updated NoC topology resulting in an incremental modification of the NoC in response to the update by changing existing components in the initial NoC topology, which becomes outdated and results in at least one of an unnecessary element and an unnecessary connection;
removing at least one of the unnecessary element and the unnecessary connection;
generating an updated NoC topology that combines the initial NoC topology with the incremental updated NoC topology that satisfies the update; and
providing a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from topology modifications.