US 12,348,256 B2
Sampler circuit for high speed serializer/deserializer
Anindita Borah, Santa Clara, CA (US); Ramsin Ziazadeh, San Jose, CA (US); and Ashwin Ramachandran, Santa Clara, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 29, 2023, as Appl. No. 18/478,198.
Prior Publication US 2025/0112661 A1, Apr. 3, 2025
Int. Cl. H04B 1/38 (2015.01); H03F 3/19 (2006.01); H03K 17/56 (2006.01)
CPC H04B 1/38 (2013.01) [H03F 3/19 (2013.01); H03K 17/56 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a differential input circuit having a first input at a first capacitor terminal and a second input
at a second capacitor terminal, the differential input circuit including:
a first transistor having a first transistor control terminal and first and second terminals; and
a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together;
a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal;
a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal;
a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal; and
a differential output circuit having a first output at a first inverter output, having a second output at a second inverter output, having a third transistor control terminal coupled to the second terminal of the first transistor, and having a fourth transistor control terminal coupled to the second terminal of the second transistor.