| CPC H03L 7/0812 (2013.01) [H03K 5/00006 (2013.01); H03K 2005/00019 (2013.01)] | 20 Claims |
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1. A frequency multiplier comprising:
a first digitally controlled delay line (DCDL) configured to receive a first clock signal and generate a second clock signal by changing a phase of the first clock signal;
a multiplying delay-locked loop (MDLL) configured to receive the second clock signal and generate a third clock signal by multiplying a frequency of the second clock signal; and
a DCDL calibration circuit configured to receive the second clock signal and generate a gain signal for adjusting a gain of the first DCDL,
wherein a difference between a maximum delay and a minimum delay of the first DCDL is substantially equal to a period of the third clock signal,
wherein the MDLL is further configured to output a plurality of clock signals having substantially different phases.
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