US 12,348,232 B2
Delay control circuit, semiconductor memory device, and delay control method
Shinya Okuno, Yokohama (JP)
Assigned to WINDBOND ELECTRONICS CORP., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Jul. 6, 2023, as Appl. No. 18/348,009.
Claims priority of application No. 2022-108866 (JP), filed on Jul. 6, 2022.
Prior Publication US 2024/0014823 A1, Jan. 11, 2024
Int. Cl. G11C 11/40 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); H03L 7/081 (2006.01); H03L 7/085 (2006.01)
CPC H03L 7/0812 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); H03L 7/085 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A delay control circuit, comprising:
a DLL control circuit, configured to determine a delay amount based on a phase difference between an input clock signal and an output clock signal;
a delay line circuit, configured to delay the input clock signal to generate the output clock signal based on the delay amount; and
a N-value detection circuit, configured to perform an N-value detection operation when the input clock signal and the output clock signal are synchronized, wherein the N-value detection operation is configured to detect a number of delayed clock cycles from the input clock signal to the output clock signal;
wherein the DLL control circuit is configured to determine whether the delay control circuit is in an overflow state by determining whether the delay amount exceeds a predetermined delay amount of the delay line circuit, wherein when it is determined that the delay control circuit is in the overflow state, a signal indicating the overflow state is output to the N-value detection circuit;
wherein when the N-value detection circuit receives the signal indicating the overflow state, the N-value detection circuit does not perform the N-value detection operation, but instead sets the number of delayed clock cycles to a predetermined value.