US 12,348,224 B2
Programmable logic block with multiple types of programmable arrays and flexible clock selection
Mark Wallis, Mouans Sartoux (FR); Jean-Francois Link, Trets (FR); and Joran Pantel, Marseilles (FR)
Assigned to STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed by STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed on Feb. 7, 2024, as Appl. No. 18/435,913.
Application 18/435,913 is a continuation of application No. 17/861,067, filed on Jul. 8, 2022, granted, now 11,942,935.
Prior Publication US 2024/0178842 A1, May 30, 2024
Int. Cl. H03K 19/17724 (2020.01); H03K 19/173 (2006.01); H03K 19/17736 (2020.01); H03K 19/17748 (2020.01); H03K 19/20 (2006.01)
CPC H03K 19/17724 (2013.01) [H03K 19/1737 (2013.01); H03K 19/1774 (2013.01); H03K 19/17744 (2013.01); H03K 19/20 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a programmable logic block, including:
a programmable logic array including first logic cells each having a first architecture, wherein each first logic cell has only one programmable memory;
a field programmable gate array including second logic cells each having a second architecture different than the first architecture, wherein each second logic cell has multiple programmable memories; and
an interface coupled to the programmable logic array and including a plurality of first registers that store data corresponding to a logical configuration of the programmable logic array.