US 12,348,220 B2
Nitride semiconductor module
Hirotaka Otake, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Jul. 24, 2023, as Appl. No. 18/357,187.
Claims priority of application No. 2022-119515 (JP), filed on Jul. 27, 2022.
Prior Publication US 2024/0039523 A1, Feb. 1, 2024
Int. Cl. H03K 17/00 (2006.01); H01L 23/31 (2006.01); H03K 17/041 (2006.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01); H03K 17/687 (2006.01)
CPC H03K 17/04106 (2013.01) [H01L 23/3171 (2013.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01); H10D 64/111 (2025.01); H03K 17/687 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A nitride semiconductor module, comprising:
a nitride semiconductor device that forms a transistor; and
a control circuit that is configured to control the nitride semiconductor device,
wherein the nitride semiconductor device includes:
an electron transit layer composed of a nitride semiconductor;
an electron supply layer arranged on the electron transit layer and composed of a nitride semiconductor having a band gap that is larger than that of the electron transit layer;
a source electrode, a gate electrode, and a drain electrode that are arranged on the electron supply layer;
a passivation layer that covers the electron supply layer and the gate electrode; and
a control electrode arranged on the passivation layer between the gate electrode and the drain electrode,
wherein the control circuit is configured to generate:
a first control voltage that is variable between a first voltage level and a second voltage level that is lower than the first voltage level to control a voltage applied between the gate electrode and the source electrode; and
a second control voltage that is variable between a third voltage level and a fourth voltage level that is lower than the third voltage level to apply between the control electrode and the source electrode, and
wherein the control circuit is configured to generate the first control voltage and the second control voltage so that, during a turn-off operation of the transistor, a shifting completion time of the second control voltage from the third voltage level to the fourth voltage level is earlier than a shifting completion time of the first control voltage from the first voltage level to the second voltage level.