US 12,348,009 B2
Power overlay architecture
Liqiang Yang, Pompano Beach, FL (US); Richard Anthony Eddins, Margate, FL (US); Robert Lloyd George, Delray Beach, FL (US); and Darrell Lee Grimes, Boca Raton, FL (US)
Assigned to GE AVIATION SYSTEMS LLC, Grand Rapids, MI (US)
Filed by GE AVIATION SYSTEMS LLC, Grand Rapids, MI (US)
Filed on Aug. 2, 2023, as Appl. No. 18/363,946.
Application 18/363,946 is a continuation of application No. 17/232,877, filed on Apr. 16, 2021, granted, now 11,757,264.
Application 17/232,877 is a continuation of application No. 16/402,914, filed on May 3, 2019, granted, now 10,985,537, issued on Apr. 20, 2021.
Claims priority of provisional application 62/731,369, filed on Sep. 14, 2018.
Prior Publication US 2023/0378725 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H02B 1/04 (2006.01); B64D 33/00 (2006.01); H02B 1/24 (2006.01); H02M 7/00 (2006.01); H05K 1/18 (2006.01)
CPC H02B 1/04 (2013.01) [B64D 33/00 (2013.01); H02B 1/24 (2013.01); H02M 7/003 (2013.01); H05K 1/181 (2013.01); H05K 2201/10053 (2013.01); H05K 2201/10166 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A modular power overlay architecture, comprising:
a first set of power overlay tiles defining a substantially planar arrangement of power switching components arranged on a first substrate and defining a first planar footprint;
a second set of power overlay tiles defining a substantially planar arrangement of power switching components arranged on a second substrate and defining a second planar footprint, the second planar footprint equal to the first planar footprint; and
a housing configured to receive the first set of power overlay tiles and the second set of power overlay tiles in a parallel arrangement where the first planar footprint and second planar footprint are in an overlying arrangement;
wherein each tile of the first set of power overlay tiles defines a first end having a set of terminals, and wherein each tile of the second set of power overlay tiles defines a first end having a set of terminals, and wherein each terminal of the set of terminals includes a first conductive layer, a second conductive layer, and a non-conductive layer separating the first conductive layer from the second conductive layer.