| CPC H01L 25/18 (2013.01) [H01L 23/481 (2013.01); H01L 23/49822 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08146 (2013.01)] | 20 Claims |
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1. A semiconductor package, comprising:
a first semiconductor chip including a first semiconductor substrate and a plurality of first through electrodes, the first semiconductor substrate having an active surface and an inactive surface, and the plurality of first through electrodes passing through the first semiconductor substrate;
a plurality of second semiconductor chips each including a second semiconductor substrate and a plurality of second through electrodes, the second semiconductor substrate having an active surface and an inactive surface, and the plurality of second through electrodes passing through the second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip and having a same vertical height as each other, wherein the active surface of the second semiconductor substrate faces the inactive surface of the first semiconductor substrate;
a plurality of coupling pads disposed between the first semiconductor chip and the plurality of second semiconductor chips and configured to electrically connect the plurality of first through electrodes to the plurality of second through electrodes;
a plurality of chip coupling insulation layers disposed between the first semiconductor chip and the plurality of second semiconductor chips and at least partially surrounding the plurality of coupling pads;
at least one supporting dummy substrate stacked on the plurality of second semiconductor chips; and
at least one supporting coupling insulation layer disposed on a bottom surface of the at least one supporting dummy substrate,
wherein each of the plurality of second semiconductor chips has a same warpage shape that bulges in one direction.
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