US 12,347,818 B2
Logic die in a multi-chip package having a configurable physical interface to on-package memory
Narasimha Lanka, Dublin, CA (US); Lohit Yerva, Mountain View, CA (US); Mohammad Rashid, San Jose, CA (US); and Kuljit S. Bains, Olympia, WA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/213,791.
Prior Publication US 2021/0225827 A1, Jul. 22, 2021
Int. Cl. H01L 25/18 (2023.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 23/5381 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 25/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/0652 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A multi-chip device comprising:
a memory die;
a logic die including a memory controller and a memory interface to connections between the memory die and the logic die;
a mirrored logic die mirrored along a mirror plane of the logic die, the connections mismatched between the memory die and the mirrored logic die;
the memory interface to configure the connections between the memory die and the logic die, including to configure mismatched connections between the memory die and the mirrored logic die, using a channel mapping to map a memory die channel bump matrix to respective logic die and mirrored logic die channel bump matrices; and
the memory controller to route channel signals transmitted on channel bumps between the memory die and the respective logic die and mirrored logic die based on the configured connections and configured mismatched connections.