US 12,347,817 B2
Semiconductor device package having warpage control
Heh-Chang Huang, Hsinchu (TW); Fu-Jen Li, Hsinchu (TW); Pei-Haw Tsao, Tai-chung (TW); and Shyue-Ter Leu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 9, 2024, as Appl. No. 18/407,760.
Application 18/407,760 is a division of application No. 17/370,282, filed on Jul. 8, 2021, granted, now 11,978,729.
Prior Publication US 2024/0145448 A1, May 2, 2024
Int. Cl. H01L 25/16 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/16 (2013.01) [H01L 21/563 (2013.01); H01L 23/3135 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/50 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device package, comprising:
a package substrate having a first surface and a second surface opposite to the first surface;
a plurality of integrated passive devices bonded to the first surface;
a first underfill element disposed over the first surface and surrounding the plurality of integrated passive devices, wherein the first underfill element extends onto a sidewall of each integrated passive device of the plurality of integrated passive devices;
a first molding layer disposed over the first surface and surrounding the plurality of integrated passive devices and the first underfill element, wherein the first molding layer has a different composition than the first underfill element;
a second molding layer disposed over the plurality of integrated passive devices and the first molding layer and surrounding the plurality of integrated passive devices, wherein the second molding layer has a different composition than the first molding layer;
a semiconductor die bonded to the second surface;
a second underfill element disposed over the second surface and surrounding the semiconductor die;
a third molding layer disposed over the second surface and surrounding the semiconductor die and the second underfill element, wherein the third molding layer has a different composition than the second underfill element, wherein openings are formed in the third molding layer to expose contact pads formed on the second surface of the package substrate; and
a plurality of conductive bumps disposed in the openings and in direct contact to the contact pads, wherein a thickness of each of the plurality of conductive bumps is greater than a thickness of the third molding layer in a direction perpendicular to the second surface of the package substrate.