US 12,347,816 B2
Integrated circuit package with decoupling capacitors
Naly Guo, Santa Clara, CA (US); Jerry Jia, Santa Clara, CA (US); Xiuzhuang Yang, Santa Clara, CA (US); and Cindy Cui, Santa Clara, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by Nvidia Corporation, Santa Clara, CA (US)
Filed on Feb. 2, 2022, as Appl. No. 17/591,084.
Claims priority of application No. 202110413801.0 (CN), filed on Apr. 16, 2021.
Prior Publication US 2022/0336430 A1, Oct. 20, 2022
Int. Cl. H01L 25/16 (2023.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H10D 1/68 (2025.01)
CPC H01L 25/16 (2013.01) [H01L 23/49827 (2013.01); H01L 23/5385 (2013.01); H01L 24/16 (2013.01); H10D 1/68 (2025.01); H01L 2224/16227 (2013.01); H01L 2224/73265 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit package, comprising:
a substrate having a first surface;
a circuit die coupled to the first surface of the substrate;
a decoupling capacitor coupled to the first surface of the substrate;
a power trace coupled to the first surface of the substrate and connected to the circuit die and to the decoupling capacitor; and
a second type of decoupling capacitor, the second types decoupling capacitor mounted to the second surface of the substrate in an opening in a second surface of the substrate, wherein the decoupling capacitor is part of a first set of decoupling capacitors and the power trace is electrically connected to each of the decoupling capacitors in the first set to form a first power island.