US 12,347,802 B2
Die corner removal for underfill crack suppression in semiconductor die packaging
Wei-Yu Chen, Hsinchu (TW); Chi-Yang Yu, Zhongli (TW); Kuan-Lin Ho, Hsinchu (TW); Chin-Liang Chen, Kaohsiung (TW); Yu-Min Liang, Zhongli (TW); and Jiun Yi Wu, Zhongli (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,554.
Application 18/446,554 is a division of application No. 17/205,669, filed on Mar. 18, 2021, granted, now 11,824,032.
Prior Publication US 2023/0387061 A1, Nov. 30, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/20 (2013.01) [H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 23/3185 (2013.01); H01L 23/3192 (2013.01); H01L 24/16 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 24/14 (2013.01); H01L 2224/13 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/14131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/19 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/221 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/73217 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/92125 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1437 (2013.01)] 20 Claims
OG exemplary drawing
 
6. A method of forming a chip package structure, the method comprising:
forming a reconstituted wafer comprising a two-dimensional array of redistribution structures, a two-dimensional array of semiconductor dies, and a molding compound matrix;
forming a two-dimensional array of chamfer regions in the reconstituted wafer, wherein each of the chamfer regions comprises a respective set of angled surfaces; and
dicing the reconstituted wafer after formation of the two-dimensional array of chamfer regions in the reconstituted wafer, wherein a fan-out package comprising a diced portion of the reconstituted wafer is formed, wherein the fan-out package comprises at least one semiconductor die which is a subset of the semiconductor dies, an epoxy molding compound (EMC) die frame comprising a patterned portion of the EMC matrix and laterally surrounding the at least one semiconductor die, and a redistribution structure located on horizontal surfaces of the at least one semiconductor die and the EMC die frame, wherein a first horizontal surface of the redistribution structure and vertical surfaces of the EMC die frame are connected via angled surfaces which include surface segments of the EMC die frame that are not horizontal and not vertical; and
attaching the fan-out package to a package substrate employing an array of solder material portions.