US 12,347,798 B2
Semiconductor device, manufacturing method, solid state image sensor, and electronic equipment
Masaki Haneda, Kanagawa (JP)
Assigned to Sony Group Corporation, Tokyo (JP)
Filed by SONY GROUP CORPORATION, Tokyo (JP)
Filed on Aug. 25, 2023, as Appl. No. 18/238,082.
Application 18/238,082 is a continuation of application No. 17/180,359, filed on Feb. 19, 2021, granted, now 11,776,923.
Application 17/180,359 is a continuation of application No. 16/830,916, filed on Mar. 26, 2020, granted, now 10,950,637, issued on Mar. 16, 2021.
Application 16/830,916 is a continuation of application No. 16/297,167, filed on Mar. 8, 2019, granted, now 10,615,210, issued on Apr. 7, 2020.
Application 16/297,167 is a continuation of application No. 15/574,207, granted, now 10,332,927, issued on Jun. 25, 2019, previously published as PCT/JP2016/063630, filed on May 6, 2016.
Claims priority of application No. 2015-104705 (JP), filed on May 22, 2015.
Prior Publication US 2023/0402411 A1, Dec. 14, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/3205 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2023.01); H10F 39/00 (2025.01); H10F 99/00 (2025.01)
CPC H01L 24/05 (2013.01) [H01L 21/3205 (2013.01); H01L 21/768 (2013.01); H01L 23/522 (2013.01); H01L 23/532 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 24/89 (2013.01); H01L 25/0657 (2013.01); H10F 39/018 (2025.01); H10F 39/809 (2025.01); H10F 39/811 (2025.01); H10F 99/00 (2025.01); H01L 24/03 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/03616 (2013.01); H01L 2224/05007 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05618 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05657 (2013.01); H01L 2224/0566 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08121 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80009 (2013.01); H01L 2224/80097 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/80948 (2013.01); H01L 2224/80986 (2013.01); H01L 2924/01012 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01023 (2013.01); H01L 2924/01025 (2013.01); H01L 2924/0104 (2013.01); H01L 2924/05442 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first section including a first semiconductor substrate and a first wiring layer;
a second section including a second semiconductor substrate and a second wiring layer, wherein the first section and the second section are stacked; and
a film disposed at an interface between the first section and the second section,
wherein the first wiring layer includes a first connection pad and a first insulating film,
wherein the second wiring layer includes a second connection pad and a second insulating film,
wherein a first portion of the first connection pad contacts a first portion of the second connection pad,
wherein a second portion of the first connection pad contacts a first portion of the film,
wherein a second portion of the second connection pad contacts a second portion of the film,
wherein the film includes a third portion that contacts the first insulating film and the second insulating film, and
wherein the first connection pad is offset from the second connection pad in a direction that is parallel to the interface between the first section and the second section.