US 12,347,793 B2
Semiconductor package
Chin-Hua Wang, New Taipei (TW); Shu-Shen Yeh, Taoyuan (TW); Yu-Sheng Lin, Hsinchu County (TW); Po-Yao Lin, Hsinchu County (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 23, 2023, as Appl. No. 18/518,466.
Application 18/518,466 is a continuation of application No. 17/874,308, filed on Jul. 27, 2022, granted, now 11,862,580.
Application 17/874,308 is a continuation of application No. 17/152,797, filed on Jan. 20, 2021, granted, now 11,450,622, issued on Sep. 20, 2022.
Prior Publication US 2024/0088063 A1, Mar. 14, 2024
Int. Cl. H01L 23/12 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 23/3677 (2013.01); H01L 23/49816 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a wiring substrate having a first surface and a second surface opposite to the first surface;
a semiconductor component disposed on the first surface of the wiring substrate;
conductor terminals disposed on the second surface of the wiring substrate; and
a bottom stiffener disposed on the second surface of the wiring substrate, wherein a lateral size of the bottom stiffener is smaller than a pitch of the conductor terminals.