US 12,347,789 B2
Air-core transformer package with ferrite electro-magnetic interference (EMI) shielding of integrated-circuit (IC) chip
Chik Wai (David) Ng, Hong Kong (HK); Kwun Yuan (Godwin) Ho, Hong Kong (HK); Ki Hin (Gary) Choi, Hong Kong (HK); Tin Ho (Andy) Wu, Hong Kong (HK); and Wai Kit (Victor) So, Hong Kong (HK)
Assigned to HIGH TECHNOLOGY LIMITED, Hong Kong (HK)
Filed by High Tech Technology Limited, Hong Kong (HK)
Filed on Mar. 14, 2022, as Appl. No. 17/693,576.
Prior Publication US 2023/0290736 A1, Sep. 14, 2023
Int. Cl. H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01)
CPC H01L 23/552 (2013.01) [H01L 23/49861 (2013.01); H01L 23/645 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/16221 (2013.01); H01L 2224/48249 (2013.01); H01L 2224/48257 (2013.01); H01L 2924/182 (2013.01); H01L 2924/3025 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor package with an integrated and shielded lead-frame transformer comprising:
a semiconductor chip having transistors formed in a semiconductor material and having integrated wiring integrated together on a chip substrate;
a first transformer coil having a first air core, the first transformer coil being a planar transformer that is substantially in a plane of the first transformer coil, the plane of the first transformer coil being parallel to a plane of the semiconductor chip;
a second transformer coil having a second air core, the second transformer coil being a planar transformer that is substantially in a plane of the second transformer coil, the plane of the second transformer coil being parallel to the plane of the semiconductor chip;
an upper ferrite-dielectric shield having a first ferrite layer and a first dielectric layer above the first ferrite layer and a second dielectric layer below the first ferrite layer, the first transformer coil being electrically isolated from the first ferrite layer by the second dielectric layer;
wherein the upper ferrite-dielectric shield is in a plane parallel to and between the plane of the first transformer coil and the plane of the semiconductor chip;
a third dielectric layer for electronically isolating the first transformer coil from the second transformer coil, the third dielectric layer being between the first transformer coil and the second transformer coil;
a plurality of lead-frame pads placed around a perimeter of the first transformer coil and around a perimeter of the second transformer coil and surrounding the semiconductor chip;
bonding wires that connect the semiconductor chip to the plurality of lead-frame pads;
a plurality of lead-frame risers that connect the plurality of lead-frame pads to package connectors for electrically connecting to an external system;
a first center post that connects to an inner end of the first transformer coil and is electrically connected to the semiconductor chip; and
a first lead-frame outer riser that connects an outer end of the first transformer coil to a first package connector for electrically connecting to the external system;
a second center post that connects to an inner end of the second transformer coil and connects to a second package connector for electrically connecting to the external system; and
a second lead-frame outer riser that connects an outer end of the second transformer coil to a third package connector for electrically connecting to the external system.