| CPC H01L 23/5389 (2013.01) [H01L 21/4857 (2013.01); H01L 23/49805 (2013.01); H01L 24/18 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 21/561 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 25/50 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/24226 (2013.01); H01L 2224/2518 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06589 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
system-on-integrated chips, each comprising a die stack having a base tier and stacking tiers stacked on the base tier, wherein the base tier comprises a base semiconductor die comprising a first semiconductor substrate and first through vias penetrating the first semiconductor substrate, and each of the stacking tiers comprises at least one stacking semiconductor die comprising a second semiconductor substrate and second through vias penetrating the second semiconductor substrate, a plurality of contact pads contacting the second through vias, and a passivation layer laterally covering the plurality of contact pads, wherein top surfaces of the plurality of contact pads is substantially coplanar with and substantially leveled with a top surface of the passivation layer, and the plurality of contact pads and the passivation layer are interposing between two adjacent stacking tiers of the stacking tiers, wherein a projection of the at least one stacking semiconductor die of each of the stacking tiers is entirely disposed within a projection of the base semiconductor die in a stacking direction of the base tier and the stacking tiers;
a first redistribution circuit structure, located on and electrically connected to the system-on-integrated chips, wherein the stacking tiers of each of the system-on-integrated chips are disposed between the base tier of a respective one of the system-on-integrated chips and the first redistribution circuit structure, wherein a sidewall of the first semiconductor substrate is aligned with a sidewall of the first redistribution circuit structure;
a second redistribution circuit structure, disposed between and electrically coupled to two adjacent stacking tiers of the stacking tiers of each of the system-on-integrated chips, the second redistribution circuit structure being in physical contact with the plurality of contact pads comprised in an underlying stacking tier of the two adjacent stacking tiers;
first conductive elements, directly connected on the first redistribution circuit structure, wherein the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive elements; and
conductive features, disposed over and electrically coupled to the system-on-integrated chips, wherein the system-on-integrated chips are located between the first conductive elements and the conductive features, and the conductive features are spacing away from an insulating encapsulation covering the base semiconductor die and the at least one stacking semiconductor die of each of the stacking tiers of the system-on-integrated chips,
wherein surfaces of the first conductive elements not covered by the first redistribution circuit structure and a surface of the first redistribution circuit structure exposed by the first conductive elements together constitute an outermost surface of the semiconductor device, and the conductive features are disposed over a side of the system-on-integrated chips opposing to the outermost surface.
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