US 12,347,781 B2
Semiconductor devices having penetration vias
Hakseung Lee, Seoul (KR); Jinnam Kim, Anyang-si (KR); Hyoukyung Cho, Seoul (KR); Taeseong Kim, Suwon-si (KR); and Kwangjin Moon, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 21, 2023, as Appl. No. 18/137,506.
Application 18/137,506 is a continuation of application No. 16/849,085, filed on Apr. 15, 2020, granted, now 11,664,316.
Claims priority of application No. 10-2019-0096018 (KR), filed on Aug. 7, 2019.
Prior Publication US 2023/0260916 A1, Aug. 17, 2023
Int. Cl. H01L 23/538 (2006.01)
CPC H01L 23/5384 (2013.01) [H01L 23/5385 (2013.01); H01L 2224/08146 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first semiconductor substrate having a first surface and a second surface opposite from each other;
a second semiconductor substrate having a first surface and a second surface opposite from each other;
a first circuit layer provided on the first surface of the first semiconductor substrate;
a second circuit layer provided on the first surface of the second semiconductor substrate;
a connection pad interposed between the second circuit layer and the first semiconductor substrate;
a first penetration via and a second penetration via that extend from the second surface of the first semiconductor substrate into at least a portion of the first circuit layer, the first penetration via in a first penetration hole and the second penetration via in a second penetration hole; and
a third penetration via that extends from the second surface of the second semiconductor substrate into at least a portion of the second circuit layer,
wherein a maximum width of the first penetration via is greater than a maximum width of the second penetration via,
wherein each of the first and second penetration holes comprises a first portion, a second portion, and a third portion,
wherein the first portions of the first and second penetration holes are adjacent to the second surface of the first semiconductor substrate and the second portions of the first and second penetration holes are between the first portions and the third portions of the respective first and second penetration holes, wherein a height of the first portion of the first penetration hole is greater than a height of the second portion of the first penetration hole,
wherein the first penetration hole has therein a first intermediate layer that surrounds the first penetration via, wherein a thickness of the first intermediate layer is a first thickness between a top of the first portion of the first penetration hole and a bottom of the first portion of the first penetration hole, wherein the thickness of the first intermediate layer decreases from the first thickness to a second thickness that is less than the first thickness between a top of the second portion of the first penetration hole and a bottom of the second portion of the first penetration hole, and
wherein a height of the first portion of the first penetration hole is greater than a height of the first portion of the second penetration hole.