US 12,347,779 B2
Three-dimensional memory device with source line isolation and method of making the same
Ramy Nashed Bassely Said, San Jose, CA (US); Jiahui Yuan, San Francisco, CA (US); and Lito De La Rama, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Sep. 23, 2022, as Appl. No. 17/934,676.
Prior Publication US 2024/0105622 A1, Mar. 28, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 23/535 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H01L 23/535 (2013.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a source layer comprising at least one doped semiconductor material;
alternating stacks of insulating layers and electrically conductive layers located over the source layer, extending along a first horizontal direction and laterally spaced apart from each other along the second horizontal direction by backside trenches, wherein the backside trenches comprise at least one first backside trench containing with a respective backside contact via structure comprising an electrically conductive material contacting the source layer, and at least one second backside trench containing a respective dielectric trench fill structure which extends from above the topmost surfaces of the alternating stacks to at least a bottom surface of the source layer;
memory openings, wherein each of the memory openings vertically extends through a respective one of the alternating stacks; and
memory opening fill structures located in the memory openings and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel.