| CPC H01L 23/535 (2013.01) [H01L 23/5329 (2013.01); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
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1. A semiconductor device, including:
a first structure;
a second structure including a stack structure including a first stack structure on the first structure and a second stack structure on the first stack structure, and an intermediate insulating layer covering at least a portion of the stack structure;
an insulating structure on the second structure;
a memory vertical structure penetrating the second structure;
a support vertical structure penetrating the second structure and including an air gap and a support layer defining at least a lower portion and a sidewall of the air gap;
a peripheral contact plug penetrating the second structure; and
gate contact plugs,
wherein each of the first and second stack structures includes interlayer insulating layers and gate layers alternately stacked,
wherein the gate layers are spaced apart from each other in a vertical direction in a first region and include gate pads arranged in a second region adjacent to the first region,
wherein the gate contact plugs are electrically connected to the gate pads,
wherein the memory vertical structure penetrates the stack structure in the first region,
wherein the memory vertical structure includes a slope changing portion between an uppermost gate layer among the gate layers of the first stack structure and a lowermost gate layer among the gate layers of the second stack structure,
wherein the support vertical structure penetrates at least a portion of the gate layers in the second region,
wherein the air gap of the support vertical structure includes a portion disposed on the same level as the slope changing portion of the memory vertical structure,
wherein the peripheral contact plug is spaced apart from the gate layers,
wherein the peripheral contact plug includes an upper region disposed on a level higher than an upper surface of an uppermost gate layer among the gate layers of the stack structure and a lower region disposed on a level lower than the upper surface of the uppermost gate layer among the gate layers of the stack structure,
wherein the upper region of the peripheral contact plug includes a first portion, a second portion and a connection portion disposed between the first portion and the second portion, and
wherein a side of the connection portion has a slope different from a slope of at least one of a side of the first portion and a side of the second portion.
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