US 12,347,776 B2
Integrated chip with graphene based interconnect
Shin-Yi Yang, New Taipei (TW); Meng-Pei Lu, Hsinchu (TW); Chin-Lung Chung, Taoyuan (TW); Ming-Han Lee, Taipei (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 27, 2023, as Appl. No. 18/360,012.
Application 18/360,012 is a division of application No. 17/308,361, filed on May 5, 2021, granted, now 12,218,060.
Prior Publication US 2023/0387019 A1, Nov. 30, 2023
Int. Cl. H01L 23/532 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/53276 (2013.01) [H01L 21/31053 (2013.01); H01L 21/7682 (2013.01); H01L 21/76834 (2013.01); H01L 21/76877 (2013.01); H01L 21/76886 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip comprising:
a substrate;
a metal via over the substrate;
a first conductive interconnect over the metal via; and
a second conductive interconnect over the metal via and laterally adjacent to the first conductive interconnect, wherein a cavity is directly between the first conductive interconnect and the second conductive interconnect, wherein the first conductive interconnect comprises graphene sheets and a metal intercalated between the graphene sheets, and wherein one of the graphene sheets of the first conductive interconnect is on a top surface of the metal via.