US 12,347,770 B2
One-time-programmable device structure
Yu-Hsiang Chen, Hsinchu (TW); Wen-Sheh Huang, Hsin Chu (TW); Po-Hsiang Huang, Taipei (TW); and Hsiu-Wen Hsueh, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 24, 2022, as Appl. No. 17/703,710.
Prior Publication US 2023/0307356 A1, Sep. 28, 2023
Int. Cl. H01L 23/525 (2006.01); H10B 20/25 (2023.01)
CPC H01L 23/5252 (2013.01) 20 Claims
OG exemplary drawing
 
1. An interconnect structure, comprising:
a first dielectric layer;
a first conductive feature and a second conductive feature in the first dielectric layer;
a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature;
a second ESL disposed directly on a top surface the first ESL;
a first dielectric feature extending through the first ESL and the second ESL to contact the first conductive feature;
a first conductive layer disposed on and in contact with the first dielectric feature;
a third ESL disposed over the first conductive layer;
a second dielectric layer disposed directly on top surfaces of the third ESL and the second ESL;
a first via extending through the second dielectric layer and the third ESL to contact with the first conductive layer; and
a second via extending through the second dielectric layer, the second ESL and the first ESL to contact with the second conductive feature.