US 12,347,769 B2
Resistor within a via
Chi-Han Yang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 17, 2024, as Appl. No. 18/415,086.
Application 18/415,086 is a continuation of application No. 17/446,405, filed on Aug. 30, 2021, granted, now 11,935,829.
Prior Publication US 2024/0162145 A1, May 16, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 21/321 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H10D 1/47 (2025.01)
CPC H01L 23/5228 (2013.01) [H01L 21/3212 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53257 (2013.01); H10D 1/474 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a via for a semiconductor device;
depositing a resistor layer within the via;
depositing a landing pad layer on the resistor layer; and
forming, within the via, a resistor from the resistor layer and one or more landing pads from the landing pad layer.