US 12,347,767 B2
Stacked FET contact formation
Koichi Motoyama, Clifton Park, NY (US); Ruilong Xie, Niskayuna, NY (US); Jennifer Church, Albany, NY (US); and Oleg Gluschenkov, Tannersville, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Sep. 23, 2022, as Appl. No. 17/951,739.
Prior Publication US 2024/0105590 A1, Mar. 28, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10D 86/01 (2025.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76819 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 23/53295 (2013.01); H10D 86/011 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first lower device and a second lower device on a substrate;
a first upper device over the first lower device and a second upper device over the second lower device;
a first lower contact that extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device and that extends laterally underneath the first upper device;
a second lower contact that extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device and that extends laterally underneath the second upper device; and
an insulating barrier between the first lower contact and the second lower contact.