US 12,347,763 B2
Packaging of three-dimensional integrated circuit by encapsulation with copper posts and double sided redistribution layer
Seungjae Lee, Pasadena, CA (US); Brett Sawyer, Pasadena, CA (US); and David Arlo Nelson, Fort Collins, CO (US)
Assigned to Rockley Photonics Limited, Altrincham (GB)
Appl. No. 17/757,823
Filed by ROCKLEY PHOTONICS LIMITED, Altrincham (GB)
PCT Filed Dec. 14, 2020, PCT No. PCT/EP2020/086022
§ 371(c)(1), (2) Date Jun. 21, 2022,
PCT Pub. No. WO2021/130045, PCT Pub. Date Jul. 1, 2021.
Claims priority of application No. 1919273 (GB), filed on Dec. 24, 2019.
Prior Publication US 2023/0343686 A1, Oct. 26, 2023
Int. Cl. H01L 23/498 (2006.01); G01F 1/00 (2022.01); G02B 1/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H10D 84/00 (2025.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01)
CPC H01L 23/49827 (2013.01) [H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 23/293 (2013.01); H01L 23/3107 (2013.01); H01L 23/49838 (2013.01); H01L 23/49866 (2013.01); H01L 23/538 (2013.01); H10D 84/00 (2025.01); H10D 84/038 (2025.01); H10D 88/01 (2025.01); G01F 1/00 (2013.01); G02B 1/00 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A system comprising:
a photonic integrated circuit (PIC); and
a package installed on the PIC and having a top surface and a bottom surface, and comprising:
a semiconductor die having a front surface, a back surface, and a plurality of side surfaces between the front surface and the back surface, the die comprising a plurality of vias extending from the front surface of the die to the back surface of the die;
a mold compound, on the back surface of the die;
a plurality of first conductive elements extending entirely through a portion of the mold compound on the back surface of the die to the top surface of the package;
a plurality of second conductive elements on the bottom surface of the package and entirely separated from the mold compound;
a first redistribution layer having a back surface, directly on the front surface of the die and directly connected to the plurality of vias, and a front surface opposite to the bottom surface, the first redistribution layer not extending beyond the side surfaces of the die, and the plurality of second conductive elements being directly on the front surface of the first redistribution layer and connected to the plurality of vias through the first redistribution layer; and
a second redistribution layer, directly on the back surface of the die and directly connected to the plurality of vias, the second redistribution layer not extending beyond the side surfaces of the die, and the plurality of first conductive elements being directly on the second redistribution layer and connected to the plurality of vias through the second redistribution layer,
wherein the mold compound is on the side surfaces of the die, and no portion of the mold compound is below the front surface of the die along a thickness direction of the die,
wherein only the plurality of second conductive elements directly contact the front surface of the first redistribution layer, and
wherein the second conductive elements are directly connected to the PIC.