US 12,347,759 B2
Semiconductor package and substrate for semiconductor package
Jin Mo Kwon, Yongin-si (KR); Dong Uk Kim, Seoul (KR); and Jin Hee Hong, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 2, 2022, as Appl. No. 17/590,954.
Claims priority of application No. 10-2021-0082450 (KR), filed on Jun. 24, 2021.
Prior Publication US 2022/0415774 A1, Dec. 29, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49822 (2013.01) [H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 24/48 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 25/0657 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/3512 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate;
a semiconductor chip on a first surface of the substrate; and
a plurality of external connection terminals on a second surface of the substrate, the first and second surfaces being opposite surfaces of the substrate,
wherein the substrate includes a plurality of wirings configured to electrically connect the semiconductor chip and the plurality of external connection terminals,
wherein the plurality of wirings include a first wiring, and the first wiring includes a first portion and a second portion connected to each other, the first portion overlapping with the semiconductor chip in a vertical direction that is perpendicular to the first surface of the substrate and the second portion overlapping an edge of the semiconductor chip in the vertical direction,
wherein the first portion and the second portion are at a same vertical level,
wherein the first portion has a first width and the second portion has a second width, and the second width of the second portion is greater than the first width of the first portion,
wherein the plurality of wirings include a second wiring, the second wiring at a different vertical level than the first wiring in the vertical direction, the second wiring including a third portion and a fourth portion connected to each other,
wherein the third portion and the fourth portion extend horizontally along the edge of the semiconductor chip while overlapping the edge of the semiconductor chip in the vertical direction,
wherein the third portion has a third width and the fourth portion has a fourth width, and
wherein the fourth width of the fourth portion is greater than the third width of the third portion.