US 12,347,749 B2
Semiconductor packages
Wei-Yu Chen, New Taipei (TW); An-Jhih Su, Taoyuan (TW); Der-Chyang Yeh, Hsinchu (TW); Li-Hsien Huang, Zhubei (TW); and Ming Shih Yeh, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 27, 2023, as Appl. No. 18/342,246.
Application 18/342,246 is a division of application No. 17/373,063, filed on Jul. 12, 2021, granted, now 11,728,249.
Application 16/588,345 is a division of application No. 15/907,474, filed on Feb. 28, 2018, granted, now 10,529,650, issued on Jan. 7, 2020.
Application 17/373,063 is a continuation of application No. 16/588,345, filed on Sep. 30, 2019, granted, now 11,062,978, issued on Jul. 13, 2021.
Claims priority of provisional application 62/586,431, filed on Nov. 15, 2017.
Prior Publication US 2023/0335471 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/485 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01)
CPC H01L 23/485 (2013.01) [H01L 21/4857 (2013.01); H01L 21/4867 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/5389 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/022 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/0508 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/214 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a first dielectric layer on a substrate;
forming a first opening in the first dielectric layer;
forming an under-bump metallurgy in the first opening;
depositing a second dielectric layer on the under-bump metallurgy and the first dielectric layer;
forming a second opening in the second dielectric layer;
dispensing solder paste in the second opening, the solder paste dispensed at an interface of the second dielectric layer and the under-bump metallurgy;
curing the solder paste to form a conductive ring sealing the interface of the second dielectric layer and the under-bump metallurgy; and
after curing the solder paste, forming a conductive connector extending through a center of the conductive ring, the conductive connector disposed on the conductive ring and the under-bump metallurgy.