US 12,347,748 B2
Semiconductor device and method of manufacturing the same
Yi-Bo Liao, Hsinchu (TW); Chun-Yuan Chen, Hsinchu (TW); Lin-Yu Huang, Hsinchu (TW); Yi-Hsun Chiu, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 19, 2022, as Appl. No. 17/891,384.
Prior Publication US 2024/0063093 A1, Feb. 22, 2024
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a stack of parallel metal gates formed on a first side of a substrate;
a first pair of insulation regions extending across the stack of parallel metal gates;
a second pair of insulation regions replacing two of the parallel metal gates, wherein three or more metal gates are located between the second pair of insulation regions;
a first isolated region enclosed by the first and second pairs of insulation regions;
a first via formed within the first isolated region, wherein the first via extends through a portion of a center of the three metal gates within the first isolated region; and
an insulation layer replacing the three metal gates located within the first isolated region.