US 12,347,732 B2
Systems and methods for mitigating crack propagation in semiconductor die manufacturing
Wei Yeeng Ng, Boise, ID (US); Rajesh Balachandran, Douglas (IE); Frank Speetjens, Boise, ID (US); Andrew L. Li, Boise, ID (US); Sukhdeep Kaur, Boise, ID (US); and Sangeetha P. Komanduri, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 24, 2023, as Appl. No. 18/306,137.
Application 18/306,137 is a division of application No. 17/137,135, filed on Dec. 29, 2020, granted, now 11,637,040.
Prior Publication US 2023/0260840 A1, Aug. 17, 2023
Int. Cl. H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/28 (2006.01)
CPC H01L 21/78 (2013.01) [H01L 23/28 (2013.01); H01L 23/562 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor wafer comprising:
a semiconductor wafer substrate that has an active surface and a back surface opposite the active surface;
active components in an active region at the active surface; and
a plurality of holes extending from the back surface towards the active surface, wherein the plurality of holes have bottom surfaces at an intermediate depth within the semiconductor wafer substrate spaced vertically apart from the active region, and the plurality of holes are configured to prevent a crack in the semiconductor wafer substrate from propagating longitudinally across the semiconductor wafer substrate, wherein the plurality of holes include:
a plurality of first holes arranged in a first pattern having a first hole density; and
a plurality of second holes arranged in a second pattern having a second hole density less than the first hole density.