US 12,347,730 B2
Method of manufacturing semiconductor structure having vias with different dimensions
Shing-Yih Shih, New Taipei (TW); and Chih-Ching Lin, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on May 12, 2022, as Appl. No. 17/742,959.
Prior Publication US 2023/0369210 A1, Nov. 16, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 23/48 (2006.01)
CPC H01L 21/76898 (2013.01) [H01L 23/481 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer;
providing a second wafer including a second substrate, a second dielectric layer over the second substrate, and a second conductive pad surrounded by the second dielectric layer;
bonding the first dielectric layer to the second dielectric layer;
disposing a passivation over the second wafer;
forming a patterned photoresist layer over the passivation, wherein the patterned photoresist layer includes a first through hole and a first indentation;
removing a first portion of the passivation exposed through the first through hole to form a first opening, and removing a second portion of the passivation under the first indentation to form a first recess;
removing a third portion of the second substrate exposed through the first opening to form a second recess;
removing a fourth portion of the passivation under the first recess to form a second opening;
removing a fifth portion of the second substrate under the second recess to form a third opening, and removing a sixth portion of the second substrate exposed through the second opening to form a fourth opening;
removing a seventh portion of the second dielectric layer exposed through the third opening to at least partially expose the second conductive pad, and removing an eighth portion of the second dielectric layer and a ninth portion of the first dielectric layer exposed through the fourth opening to at least partially expose the first conductive pad, thereby forming a first trench extending through the second wafer and the passivation and partially through the first dielectric layer, and thereby forming a second trench extending through the passivation and the second substrate and partially through the second dielectric layer;
removing the patterned photoresist layer;
disposing a dielectric liner over the passivation and conformal to the first trench and the second trench; and
forming a first conductive via within the first trench and a second conductive via within the second trench.