US 12,347,726 B2
Interconnect structures and methods of forming the same
Wei-Ren Wang, New Taipei (TW); Jen Hung Wang, Hsinchu (TW); and Tze-Liang Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 31, 2022, as Appl. No. 17/710,531.
Claims priority of provisional application 63/275,523, filed on Nov. 4, 2021.
Prior Publication US 2023/0135172 A1, May 4, 2023
Int. Cl. H01L 21/768 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H01L 21/76832 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/7685 (2013.01); H01L 21/76879 (2013.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first dielectric layer over an integrated circuit device;
forming a first conductive feature in the first dielectric layer;
selectively depositing an inhibitor material over the first conductive feature;
selectively depositing an etch-resistant layer over the first dielectric layer adjacent the inhibitor material;
removing the inhibitor material to form a first opening exposing the first conductive feature;
selectively depositing a capping layer over the first conductive feature;
forming an etch stop layer over the etch-resistant layer and the capping layer;
forming a second dielectric layer over the etch stop layer;
etching the second dielectric layer and the etch stop layer to form a second opening exposing the capping layer; and
forming a second conductive feature in the second opening and electrically coupled to the first conductive feature through the capping layer.