US 12,347,725 B2
Semiconductor structure with material modification and low resistance plug
Mrunal A. Khaderbad, Hsinchu (TW); and Akira Mineji, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co. Ltd., Hsin-Chu (TW)
Filed on Nov. 20, 2023, as Appl. No. 18/514,164.
Application 17/321,292 is a division of application No. 16/380,662, filed on Apr. 10, 2019, granted, now 11,018,053, issued on May 25, 2021.
Application 18/514,164 is a continuation of application No. 17/321,292, filed on May 14, 2021, granted, now 11,854,871.
Claims priority of provisional application 62/691,695, filed on Jun. 29, 2018.
Prior Publication US 2024/0087952 A1, Mar. 14, 2024
Int. Cl. H01L 21/768 (2006.01); H01L 21/3115 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01)
CPC H01L 21/76831 (2013.01) [H01L 21/76825 (2013.01); H01L 21/7684 (2013.01); H01L 21/76879 (2013.01); H01L 23/522 (2013.01); H01L 23/53266 (2013.01); H10D 64/01 (2025.01); H01L 21/31155 (2013.01); H10D 30/6219 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a semiconductor substrate;
a source/drain feature over the semiconductor substrate;
a gate stack over the semiconductor substrate and adjacent the source/drain feature;
a dielectric layer over the semiconductor substrate and surrounding the source/drain feature and the gate stack;
a first metal plug over the source/drain feature and buried in the dielectric layer, wherein the dielectric layer includes a first hydrophobic sidewall having a vertical portion and a horizontal portion, the vertical portion interfacing the first metal plug and the horizontal portion extends along a top surface of the dielectric layer; and
a second metal plug penetrating through the dielectric layer to land on the gate stack, wherein the horizontal portion of the first hydrophobic sidewall directly contacts the second metal plug.