US 12,347,718 B2
Wafer conveyance unit and wafer conveyance method
Akira Shimase, Hamamatsu (JP); Toshimichi Ishizuka, Hamamatsu (JP); and Masataka Ikesu, Hamamatsu (JP)
Assigned to HAMAMATSU PHOTONICS K.K., Hamamatsu (JP)
Appl. No. 17/772,596
Filed by HAMAMATSU PHOTONICS K.K., Hamamatsu (JP)
PCT Filed Nov. 9, 2020, PCT No. PCT/JP2020/041755
§ 371(c)(1), (2) Date Apr. 28, 2022,
PCT Pub. No. WO2021/149330, PCT Pub. Date Jul. 29, 2021.
Claims priority of application No. 2020-009273 (JP), filed on Jan. 23, 2020.
Prior Publication US 2022/0406644 A1, Dec. 22, 2022
Int. Cl. H01L 21/687 (2006.01); H01L 21/67 (2006.01); H01L 21/677 (2006.01)
CPC H01L 21/68728 (2013.01) [H01L 21/67288 (2013.01); H01L 21/67706 (2013.01); H01L 21/68721 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A wafer conveyance unit configured to convey a wafer while holding the wafer in a semiconductor failure analysis apparatus, the wafer conveyance unit comprising:
a fixing unit configured to fix a wafer at a predetermined observation position; and
a conveyance unit configured to convey the wafer to the observation position while holding the wafer, the conveyance unit including:
a plurality of holding members provided so as to face a side surface of the wafer and holding the wafer by sandwiching a peripheral portion of the wafer with the plurality of holding members; and
a ring portion that partitions a housing space for housing the wafer,
wherein the ring portion is provided with the plurality of holding members that protrude toward the housing space, and
wherein the plurality of holding members comprise:
a first holding member comprising one or a plurality of protruding portions configured to abut on a peripheral portion of the wafer, and
a second holding member spaced from the first holding member and comprising one or a plurality of the protruding portions, and
wherein a direction of a force applied to the wafer by the first holding member configured to sandwich the wafer and a direction of a force applied to the wafer by the second holding member configured to sandwich the wafer are opposite to each other.