US 12,347,708 B2
Inspection apparatus, manufacturing method of integrated circuit, and inspection method
Tsung-Fu Tsai, Changhua County (TW); and Szu-Wei Lu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 16, 2022, as Appl. No. 17/696,828.
Prior Publication US 2023/0298917 A1, Sep. 21, 2023
Int. Cl. H01L 21/67 (2006.01); G01R 31/26 (2020.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01)
CPC H01L 21/67288 (2013.01) [G01R 31/2601 (2013.01); H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 22/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A manufacturing method of an integrated circuit, comprising:
providing a semiconductor wafer having an active surface and a rear surface opposite to the active surface;
pre-bonding dies onto the semiconductor wafer, wherein each die has an active surface and a rear surface opposite to the active surface, and the active surface of the semiconductor wafer and the active surfaces of the dies form a bonding surface;
performing a first inspection process for inspecting the bonding surface, comprising:
transferring the semiconductor wafer and the dies onto a first testing stage, where the first testing stage has a cavity and the rear surfaces of the dies face the cavity;
clamping the semiconductor wafer and the dies to the first testing stage by a testing clamp;
inspecting the bonding surface by a first transducer, wherein a first testing fluid is provided between the first transducer and the rear surface of the semiconductor wafer; and
drying the rear surface of the semiconductor wafer;
performing a thermal process on the dies and the semiconductor wafer after the first inspection process, so as to securely bond the dies onto the semiconductor wafer;
forming an encapsulant on the semiconductor wafer to laterally encapsulate the dies;
forming an interconnection structure and conductive vias over the rear surface of the semiconductor wafer; and
singulating the semiconductor wafer and the encapsulant.