US 12,347,688 B2
Lateral transistor with self-aligned body implant
Achim Gratz, Dresden (DE); Jürgen Faul, Radebeul (DE); and Swapnil Pandey, Dresden (DE)
Assigned to Infineon Technologies Dresden GmbH & Co. KG, Dresden (DE)
Filed by Infineon Technologies Dresden GmbH & Co. KG, Dresden (DE)
Filed on Jan. 2, 2024, as Appl. No. 18/401,957.
Application 18/401,957 is a division of application No. 17/357,369, filed on Jun. 24, 2021, granted, now 11,887,852.
Claims priority of application No. 102020117171.4 (DE), filed on Jun. 30, 2020.
Prior Publication US 2024/0136189 A1, Apr. 25, 2024
Prior Publication US 2024/0234149 A9, Jul. 11, 2024
Int. Cl. H01L 21/265 (2006.01); H01L 21/266 (2006.01); H10D 18/00 (2025.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 62/17 (2025.01); H10D 64/66 (2025.01); H10D 84/00 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/60 (2025.01); H10F 77/20 (2025.01); H10F 77/60 (2025.01)
CPC H01L 21/265 (2013.01) [H01L 21/2652 (2013.01); H01L 21/266 (2013.01); H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01); H10D 62/393 (2025.01)] 7 Claims
OG exemplary drawing
 
1. A lateral transistor, comprising:
a semiconductor substrate;
a body region formed by dopant implantation in the semiconductor substrate, the body region having a lateral boundary;
a dielectric layer arranged over the semiconductor substrate; and
a structured gate layer arranged over the dielectric layer,
wherein the structured gate layer overlaps the body region in the semiconductor substrate in a zone between the lateral boundary of the body region and a gate edge of the structured gate layer,
wherein the lateral boundary of the body region is a boundary defined by dopant implantation,
wherein a lower boundary of the body region in the semiconductor substrate has a stepped profile, and wherein a length of the stepped profile corresponds to the length of the zone.