US 12,347,687 B2
Etch rate modulation of FinFET through high-temperature ion implantation
Qintao Zhang, Mt Kisco, NY (US); Rajesh Prasad, Lexington, MA (US); and Jun-Feng Lu, Shanghai (CN)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Appl. No. 18/013,675
Filed by Applied Materials, Inc., Santa Clara, CA (US)
PCT Filed Aug. 21, 2020, PCT No. PCT/CN2020/110530
§ 371(c)(1), (2) Date Dec. 29, 2022,
PCT Pub. No. WO2022/036695, PCT Pub. Date Feb. 24, 2022.
Prior Publication US 2023/0369050 A1, Nov. 16, 2023
Int. Cl. H01L 21/265 (2006.01); H01L 21/311 (2006.01)
CPC H01L 21/265 (2013.01) [H01L 21/31116 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a semiconductor device within a process chamber, the semiconductor device comprising:
a plurality of fins extending from a buried oxide layer; and
a masking layer atop each of the plurality of fins;
performing a high-temperature ion implant to an exposed top surface of the buried oxide layer; and
performing an etch process to remove the masking layer from atop each of the plurality of fins, without removing the buried oxide layer.