US 12,347,685 B2
Semiconductor structure and method for fabricating same
Yexiao Yu, Hefei (CN); Zhongming Liu, Hefei (CN); Zhong Kong, Hefei (CN); and Longyang Chen, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 8, 2023, as Appl. No. 18/151,465.
Application 18/151,465 is a continuation of application No. PCT/CN2022/070399, filed on Jan. 5, 2022.
Claims priority of application No. 202111402935.9 (CN), filed on Nov. 24, 2021.
Prior Publication US 2023/0162981 A1, May 25, 2023
Int. Cl. H01L 21/033 (2006.01); H01L 21/311 (2006.01); H10B 12/00 (2023.01)
CPC H01L 21/0337 (2013.01) [H01L 21/31144 (2013.01); H10B 12/01 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, a plurality of active areas arranged at intervals being provided in the substrate, and the substrate being covered with an insulating layer and a barrier layer stacked sequentially;
forming a plurality of first trenches arranged at intervals in the barrier layer, each of the plurality of first trenches extending along a first direction and penetrating through the barrier layer;
forming a filling layer in each of the plurality of first trenches, and forming a first mask layer on the barrier layer and the filling layer;
forming a plurality of second trenches arranged at intervals in the first mask layer, each of the plurality of second trenches extending along a second direction, and each of the plurality of second trenches exposing the filling layer; and
removing the filling layer exposed in each of the plurality of second trenches and the insulating layer corresponding to the filling layer to form a contact hole, the contact hole exposing each of the plurality of active areas.