US 12,347,681 B2
Method of forming a semiconductor device
Chia-Cheng Chen, Hsinchu (TW); Chun-Hung Wu, New Taipei (TW); Liang-Yin Chen, Hsinchu (TW); Huicheng Chang, Tainan (TW); Yee-Chia Yeo, Hsinchu (TW); Chun-Yen Chang, Hsinchu (TW); Chih-Kai Yang, Taipei (TW); Yu-Tien Shen, Tainan (TW); and Ya Hui Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,463.
Application 18/362,463 is a continuation of application No. 17/463,000, filed on Aug. 31, 2021, granted, now 11,776,810.
Prior Publication US 2023/0411156 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/0274 (2013.01) [H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device comprising:
forming a dielectric layer over a substrate;
forming a carbon-rich hard masking layer over the dielectric layer, the carbon-rich hard masking layer comprises greater than 50% carbon by atomic weight;
patterning features in the carbon-rich hard masking layer using an etching process;
performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, the directional ion beam trimming process reshaping an end of one or more features patterned in the carbon-rich hard masking layer from a triangular shape to a square shape, wherein the carbon-rich hard masking layer contains a first feature and a second feature separated by a minimum distance along a plane parallel to the major axis of the first feature and the second feature, and wherein the directional ion beam trimming process does not reduce the minimum distance separating the first feature and the second feature;
patterning the dielectric layer using the carbon-rich hard masking layer as a mask; and
forming conductive lines in the dielectric layer.