| CPC H01G 4/38 (2013.01) [H01L 23/642 (2013.01); H10D 1/043 (2025.01); H10D 1/714 (2025.01); H10D 84/212 (2025.01); H01G 4/232 (2013.01); H01G 4/30 (2013.01)] | 20 Claims |

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1. A method for fabricating a stacked vertical capacitor device, the method comprising:
embedding within a substrate a vertical capacitor element including a first polarity electrode, a second polarity electrode vertically disposed relative to the first polarity electrode, and a central capacitance region disposed between the first polarity electrode and the second polarity electrode, the vertical capacitor element having a first orientation;
laminating the vertical capacitor element with an embedding material;
exposing metallization surfaces of the vertical capacitor element;
defining one or more vias through a cross section of the substrate;
electroplating a top terminal metal plane and a bottom terminal metal plane onto the first polarity electrode and the second polarity electrode of the vertical capacitor element, and the via; and
isolating, on the top terminal metal plane, a top first polarity terminal and a top second polarity terminal, and on the bottom terminal metal plane, a bottom first polarity terminal and a bottom second polarity terminal, a first one of the vias connecting the top first polarity terminal and the bottom first polarity terminal and a second one of the vias connecting the top second polarity terminal and the bottom second polarity terminal.
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