US 12,347,519 B2
Methods for reading data from a storage buffer including delaying activation of a column select
Parthasarathy Gajapathy, Highland Village, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 14, 2022, as Appl. No. 17/966,350.
Application 17/966,350 is a continuation of application No. 15/965,263, filed on Apr. 27, 2018, granted, now 11,488,645, issued on Nov. 1, 2022.
Application 15/965,263 is a continuation of application No. 13/445,659, filed on Apr. 12, 2012, abandoned.
Prior Publication US 2023/0039948 A1, Feb. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/12 (2006.01); G11C 7/10 (2006.01); G11C 8/18 (2006.01); G11C 11/4076 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 7/1018 (2013.01); G11C 8/18 (2013.01); G11C 11/4076 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A state machine engine, comprising:
a bus interface configured to couple the state machine engine to a data bus;
a first finite state machine lattice comprising a first plurality of programmable hardware elements comprising a plurality of selectively couple-able hardware elements, wherein the first finite state machine lattice is configured to:
analyze data received by the state machine engine to generate match results between the data and the first plurality of programmable hardware elements programmed with first processing criteria to implement a first finite state machine; and
output a first state vector comprising a state of the first plurality of programmable hardware elements indicative of the match results between the first plurality of programmable hardware elements and the data to facilitate subsequent processing of the data; and
a first storage buffer coupled between the bus interface and the first finite state machine lattice, wherein the first storage buffer comprises a first portion of a memory cell array implemented in a memory device and the first storage buffer is configured to:
store the data received by the state machine engine in the first portion of the memory cell array; and
seamlessly supply the data to the first finite state machine lattice, wherein, to seamlessly supply the data, the first storage buffer is configured to:
select a first memory cell column in the first storage buffer to output a first portion of the data during a first array cycle;
select a second memory cell column in the first storage buffer to output a second portion of the data during a second array cycle; and
delay selection of a third memory cell column in the first storage buffer to delay output of a third portion of the data from the third memory cell column until at least a third array cycle that occurs two array cycles after the second array cycle to allow both the first portion of the data and the second portion of the data to be fully output from the first storage buffer prior to occurrence of the third array cycle, wherein selection of an occurrence of the third array cycle is determined based upon output operational characteristics of the first storage buffer related to output capacity of the first storage buffer.