| CPC G11C 7/08 (2013.01) [G11C 7/1069 (2013.01); G11C 7/12 (2013.01)] | 20 Claims |
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1. A memory device, comprising:
a memory array comprising a first set of column lines and a second set of column lines both extending in a first direction and a set of row lines extending in a second direction orthogonal to the first direction, each row line of the set of row lines coupled with a first set of memory cells that are coupled with the first set of column lines and with a second set of memory cells that are coupled with the second set of column lines;
a set of sense amplifiers adjacent to the memory array in the first direction and extending over a first dimension in the first direction, a first subset of the set of sense amplifiers coupled with corresponding column lines of the first set of column lines and a second subset of the set of sense amplifiers coupled with corresponding column lines of the second set of column lines, wherein the set of sense amplifiers are configured to read logic states stored in memory cells associated with a row line of the set of row lines based at least in part on an access operation for the row line; and
a counter adjacent to the set of sense amplifiers along the second direction and located within the first dimension in the first direction, wherein the counter is configured to track a quantity of access operations for the row line by incrementing a value based at least in part on the access operation for the row line, wherein, prior to incrementing the value, the value comprises the logic states read by the second subset of the set of sense amplifiers.
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