US 12,347,512 B2
Error detection, correction, and media management on a memory device
Amitava Majumdar, Boise, ID (US); Greg S. Hendrix, Boise, ID (US); Anandhavel Nagendrakumar, Boise, ID (US); Krunal Patel, Boise, ID (US); Kirthi Shenoy, Boise, ID (US); Danilo Caraccio, Milan (IT); Ankush Lal, Boise, ID (US); Frank F. Ross, Boise, ID (US); and Adam D. Gailey, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 15, 2023, as Appl. No. 18/169,621.
Claims priority of provisional application 63/408,728, filed on Sep. 21, 2022.
Prior Publication US 2024/0095120 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/20 (2006.01); G06F 11/10 (2006.01); G11C 29/00 (2006.01); G11C 29/52 (2006.01)
CPC G11C 29/52 (2013.01) [G06F 11/1048 (2013.01); G11C 29/76 (2013.01); G11C 29/789 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a transaction layer configured to interface with a host processor;
a memory controller with a physical layer configured to interface with a dynamic random-access memory (DRAM);
an error logic block (ELB) configured to identify a data read error in a data block read from DRAM and provide error correction for the data read error from the DRAM data block;
a persistent storage configured to store a historical record of memory addresses which have displayed data read errors; and
a post-package repair (PPR) logic block configured to:
identify all of: (a) whether the data read error indicates a requirement for a post-package repair (PPR) of the data block memory address where the data read error occurred, (b) whether a required repair is a soft PPR or a hard PPR, (c) whether a PPR resource is available for a required soft PPR or hard PPR, and (d) whether to make a soft PPR or a hard PPR based on the required repair and the available PPR resource; and
perform the post-package repair.