| CPC G11C 29/50004 (2013.01) [G11C 2029/5004 (2013.01)] | 20 Claims |

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1. A semiconductor device comprising:
a memory device that includes a memory cell, a page buffer, and a first switch, wherein a first end of the first switch is electrically connected to a first node located at a bonding point of the memory cell and a second end of the first switch is connected to a second node located at the page buffer; and
a memory controller that is configured to apply a pre-charge voltage to the first node and the second node during a first period, to close the first switch in a second period following the first period, and to determine whether bonding between the memory cell and the first switch is defective based on a voltage of the second node after the first switch is closed.
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