US 12,347,508 B2
Error detection pin encoding scheme to avoid maximum transitions and further improve signal integrity on high speed graphic memory interfaces
Sunil Sudhakaran, Brisbane, CA (US); Gautam Bhatia, San Mateo, CA (US); and Robert Bloemer, Sterling, MA (US)
Assigned to NVIDIA Corp., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Feb. 11, 2022, as Appl. No. 17/670,226.
Claims priority of provisional application 63/149,103, filed on Feb. 12, 2021.
Prior Publication US 2022/0262447 A1, Aug. 18, 2022
Int. Cl. G11C 29/02 (2006.01); G11C 29/12 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); H03K 19/00 (2006.01); H03M 5/20 (2006.01); H04L 1/00 (2006.01); H04L 25/49 (2006.01)
CPC G11C 29/025 (2013.01) [G11C 29/12005 (2013.01); G11C 29/1201 (2013.01); G11C 29/42 (2013.01); G11C 29/4401 (2013.01); H03K 19/0005 (2013.01); H03M 5/20 (2013.01); H04L 1/0041 (2013.01); H04L 25/4917 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A transmitter comprising:
a first encoder configured to:
generate first symbols on a plurality of data channels by applying pulse amplitude N-level modulation (PAM-N) encoding on a first subset of bits of a data burst, the first symbols generated without maximum transitions between the first symbols; and
generate second symbols on at least one optionally-activated additional data channel, the second symbols generated by applying the PAM-N encoding on a second subset of bits of the data burst, the second symbols generated without maximum transitions between the second symbols; and
a second encoder configured to:
generate third symbols on a channel for communicating error correction bits for the first subset of bits and the second subset of bits, the third symbols generated by applying hybrid PAM-N encoding on the error correction bits and a third subset of bits of the data burst, the hybrid PAM-N encoding comprising an interleaving of symbols with N voltage levels and symbols with less than N voltage levels.