US 12,347,507 B2
Method and apparatus for memory chip row hammer threat backpressure signal and host side response
Kuljit S. Bains, Olympia, WA (US); Bill Nale, Livermore, CA (US); Jongwon Lee, Hillsboro, OR (US); and Sreenivas Mandava, Los Altos, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 8, 2021, as Appl. No. 17/315,303.
Claims priority of provisional application 63/183,509, filed on May 3, 2021.
Prior Publication US 2021/0264999 A1, Aug. 26, 2021
Int. Cl. G11C 29/02 (2006.01); G11C 29/00 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/025 (2013.01) [G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/783 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory chip, comprising:
row hammer threat detection circuitry to detect a row hammer event where respective row activation counts for multiple rows of memory have concurrently reached a threshold, where the threshold indicates when the row activation count for a specific row becomes a row hammer threat;
an output coupled to a signal line; and
backpressure signal generation circuitry coupled between the row hammer threat detection circuitry and the output, the backpressure signal generation circuitry to send a backpressure signal on the signal line in response to detection of the row hammer event, the backpressure signal to indicate to a memory controller that the memory chip needs additional refresh time to internally mitigate the row hammer event.