US 12,347,504 B2
One-time-programmable memory devices
Chrong Jung Lin, Hsinchu (TW); Ya-Chin King, Hsinchu (TW); and Li-Yu Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TSING HUA UNIVERSITY, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW); and National Tsing Hua University, Hsinchu (TW)
Filed on Jun. 2, 2023, as Appl. No. 18/328,091.
Prior Publication US 2024/0404611 A1, Dec. 5, 2024
Int. Cl. G11C 17/16 (2006.01); G11C 17/18 (2006.01); H10B 20/25 (2023.01)
CPC G11C 17/16 (2013.01) [G11C 17/18 (2013.01); H10B 20/25 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first memory cell comprising:
a first select transistor;
a first diode; and
a first conductor fuse;
wherein the first diode and the first conductor fuse are coupled in series, with the first select transistor coupled to a first common node between the first diode and the first conductor fuse;
a first word line coupled to a gate of the first select transistor;
a first source line coupled to a first terminal of the first conductor fuse;
a first bit line coupled to a first source/drain of the first select transistor; and
a first current-divider line coupled to a first terminal of the first diode.